1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a test structure that may be used to determine the distinct properties of each transistor densely packed within the integrated circuit.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (xe2x80x9cn-channelxe2x80x9d) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (xe2x80x9cp-channelxe2x80x9d) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
Semiconductor fabrication involves producing a large number of identical integrated circuit devices upon a unitary semiconductor substrate in an array of rectangular elements called xe2x80x9cdicexe2x80x9d. A few of those devices may be devoted to electrical testing while a majority of the devices are individually packaged to be used as computer hips. Reserving test areas of the substrate for electrical testing is necessary to ensure that functional devices are being manufactured. Further, the properties of the test devices (or test structures) are determined to ensure that optimum device performance is being achieved for the manufactured devices. Several transistor properties, e.g., drive current, ID, and subthreshold current, IDst, may be determined using electrical testing of such test structures. Because of the increased desire to build faster and more complex integrated circuit devices, it has become necessary to form relatively small, closely spaced multiple transistors within a single integrated circuit device. Unfortunately, as the packing density of transistors within integrated circuit devices, and hence test structures increases, it becomes more difficult to electrically test a particular transistor within a dense grouping of transistors.
FIG. 1 depicts densely packed transistors arranged within and upon a test area of a substrate. Polysilicon gate conductors 12, 14, and 16 are spaced parallel to each other across a horizontal plane. Gate conductors 12, 14 and 16 are laterally spaced relatively close to each other, e.g., less than 0.3 micron apart to form, e.g., a series-connected grouping of transistors. The test area and, specifically, the gate conductors 12, 14 and 16 are used to replicate similar, series-connected transistors within the active die areas of the semiconductor wafer. Accordingly, source/drain regions 20 of the substrate which are each mutually shared by two transistors have relatively small lateral widths. Because source/drain regions 18 are not confined between closely spaced gate conductors, they have larger lateral widths than source/drain regions 20. The small distance between gate conductors 12 and 14 and between gate conductors 14 and 16 afford high speed series-connected operation of, e.g., a multiple input logic device. Contacts would not normally be formed to source/drain regions 20 since an output would not ordinarily be present from regions 20. Attempts to place contacts to source/drain regions 20, e.g., for testing a single transistor of the series-connected transistor within the test area would be difficult at best.
Contact formation involves etching a contact opening, i.e., a via, through an interlevel dielectric, followed by filling the contact opening with a conductive material. A well-known technique known as xe2x80x9clithographyxe2x80x9d is used to pattern a photosensitive film, i.e., photoresist, above the interlevel dielectric to define the region to be etched. The portions of the interlevel dielectric to be removed are exposed while those portions to be retained are protected by the photoresist which remains intact during the etch step. The lateral width (i.e., the distance between opposed lateral edges) of the contact is thus mandated by the minimum lateral dimension that can be achieved for lithographically patterned features. Unfortunately, the minimum lateral dimension that can be defined using lithography is limited by, inter alia, the resolution of the optical system (i.e., aligner or printer) used to project an image onto the photoresist. The term xe2x80x9cresolutionxe2x80x9d describes the ability of an optical system to distinguish closely spaced objects. Therefore, the lateral width of a contact formed to one of the source/drain regions 20 could not be less than the lateral distance between adjacent gate conductors, particularly since the distance between gate conductors is also dictated by lithography.
Perfect alignment of a photoresist pattern to the targeted features of a semiconductor substrate is rarely achievable. Thus, it is highly probable that the photoresist pattern used to define the region of the interlevel dielectric to be etched would be misaligned, resulting in contacts being shifted laterally from their targeted positions. If contacts were to be formed to source/drain regions 20, portions of at least two of the gate conductors 12, 14, and 16 most likely would be undesirably etched. Consequently, the original lateral width of each gate conductor would be reduced, and the etched gate conductors would no longer be positioned immediately adjacent one of the source/drain regions 20. Further, conductive material deposited into the contact openings would undesirably communicate with the etched gate conductors. An electrical short could thus be formed between the etched gate conductors and adjacent source/drain regions 20, rendering the transistors inoperable. Alternately, the contacts could only be electrically linked to the etched gate conductors, making it impossible to pass electrical signals to and receive electrical signals from source/drain regions 20 for the purpose of testing a single transistor within the series-connected chain. The distinct properties of each of the transistors employing source/drain regions 20 thus could not be determined. Forming contacts to source/drain regions 20 in order to determine the characteristics of the transistors would in effect make it impossible to determine the properties of the devices in their original configuration. Therefore, forming contacts to source/drain regions 20 would defeat the purpose of creating the contacts in the first place.
To avoid the problems incurred when forming contacts to source/drain regions aligned between closely spaced gate conductors, conventional methods have turned to other means for electrically testing the device properties. As shown in FIG. 1, contacts 22 may be formed to source/drain regions 18 without damaging adjacent gate conductors 12 and 16 since regions 18 are not bound between closely-spaced gate conductors. Source/drain regions 18 are larger in lateral dimension than the minimum lateral dimension of lithographically patterned features. Accordingly, the lateral width of each contact may be reduced significantly below that of each source/drain region 18. Thus, even if the photoresist pattern used to define the contacts is mis-aligned, some space in which the contacts may be formed still exists between the targeted contact positions and the gate conductors. Consequently, contact openings may be etched through a dielectric to source/drain regions 18 without risking the removal of portions of gate conductors 12, 14, and 16. Contacts 22 may be electrically linked to probe pads 26 by horizontally extending conductors 24 formed a spaced distance above the substrate. Another set of conductors 28 may be formed to electrically link each of the gate conductors 12, 14, and 16 to one of the probe pads 29.
Unfortunately, absent the formation of contacts to source/drain regions 20, the individual properties of each transistor belonging to the series-connected group of transistors are difficult to measure accurately using electrical testing. For example, if PMOSFET transistors are connected in series, an attempt may be made to determine ID of one of the transistors by (a) applying a voltage, xe2x88x92VDD, to gate conductors 12 and 16 to drive the corresponding transistors into saturation, (b) applying a voltage, xe2x88x92VDD, to one of the source/drain regions 18, (c) modulating a voltage, Vgs, applied to the gate conductor 14 until the corresponding transistor begins to operate (i.e., Vgs greater than VT, the threshold voltage), and (d) grounding or applying a voltage that is at least one threshold below VDD to the other of the source/drain regions 18, (i.e., the output source/drain region 18). Electrical signals may be applied to gate conductors 12, 14, and 16 and source/drain regions 18 by contacting electrical probes to the probe pads 29 electrically linked to those gate conductors and to the probe pads 26 coupled to those source/drain regions. The current passing to the output source/drain region 18 may be measured by contacting an electrical probe to the corresponding one of the probe pads 26. Although two of the series-connected transistors are operating in the saturation region at which the transistor drive current has reached its upper limit (i.e., saturation drive current, Isat), the channel regions underneath gate conductors 12 and 16 still exhibit some parasitic resistance to current flow. Consequently the current passing to the output source/drain region 18 is not the true drive current, ID, of the transistor which employs gate conductor 14. As such, the distinct characteristics of a single transistor belonging to a series-connected assembly of densely packed transistors as shown in FIG. 1 cannot be determined using conventional techniques.
It would therefore be of benefit to develop a test structure and method for determining the distinct properties of each transistor belonging to a plurality of closely spaced, series-connected transistors. Thus, a test structure is required in which contacts could be formed to the source/drain regions of a single transistor within a series-connected sequence of transistors. The test structure must therefore be one that can determine characteristics of the single transistor and not be hindered by the other transistors within the test structure and/or the other transistors within the sequence of series-connected transistors. That is, it would be desirable if sufficient connectivity can be gained to the single transistor while totally discarding effects from neighboring transistors. Accordingly, it would also be desirable to characterize the single transistor without relying on the neighboring transistors to pass current and/or voltage to and from the transistor. A test structure is thus needed which would allow current to flow to a transistor being tested in the absence of parasitic resistance created by the channel regions of the neighboring transistors within a series-connected sequence of transistors typically associated with a multiple-input logic gate. Electrical testing of such a test structure could be used to determine the true properties of a transistor within a multiple-input logic gate.
The problems outlined above are in large part solved by the test structure hereof, and a method for using the test structure to determine the distinct characteristics of each transistor arranged in a densely packed configuration with other transistors. The test structure is fabricated upon a test area of a semiconductor substrate. Closely spaced gate conductors having relatively small lateral widths, i.e., physical gate lengths, are formed above the test area, according to the design of an integrated circuit device, e.g., a multiple input logic device, which employs series-connected transistors. All of the gate conductors arranged above the test area, with the exception of the one being subjected to testing, are then etched away.
Source/drain implants which are self-aligned to the opposed sidewall surfaces of the gate conductor retained above the test area are forwarded into the substrate. Absent the other gate conductors, the resulting source/drain regions of the substrate extend laterally to an isolation region arranged within the substrate. The isolation region is spaced from the gate conductor by a distance greater than the distance between the pre-existing gate conductors. As such, the lateral width of contacts formed through an interlevel dielectric to the source/drain regions may be made significantly less than the lateral width of each source/drain region. The targeted positions of the contacts are chosen such that even if the contacts are mis-aligned they will be formed a spaced distance from the sole remaining gate conductor. Therefore, the contacts, and hence the contact openings, may be formed without being concerned that portions of the gate conductor might be etched and that the contacts might electrically communicate with the gate conductor. Accordingly, it would be less likely for an electrical short to form between the gate conductor and an adjacent source/drain region.
Advantageously, an electrical signal may be routed to the resulting transistor absent the flow of current to that transistor through the channel regions of other transistors which are connected in series to that transistor. An electrical signal may be communicated to one of the source/drain regions by applying the signal directly to a probe pad which is electrically linked to the source/drain region. Further, the properties of the resulting transistor may be determined by reading an electrical signal directly from the probe pad which is coupled to the drain region of the transistor, rather than from a probe pad coupled to a drain region of another transistor. Otherwise, the channel regions of the series-connected transistors would add resistance to the flow of current to and from the transistor being characterized, making it impossible to determine the distinct properties of that transistor. Therefore, the test structure hereof may be used to determine the true properties of a transistor, despite the transistor having been fabricated in a densely packed configuration with other series-connected transistors.
According to an embodiment of the present invention, the test structure is formed by first depositing a polysilicon layer across a gate dielectric that is arranged upon a test area of a semiconductor substrate. Portions of the polysilicon layer and the gate dielectric are then etched away to define sidewall surfaces of multiple polysilicon gate conductors dielectrically spaced above the substrate. The gate conductors are laterally spaced apart by a relatively short distance. An isolation region is arranged within the substrate a spaced distance from the xe2x80x9cendxe2x80x9d gate conductors which are not interposed between two other gate conductors. All except one of the gate conductors arranged above the test area and their underlying gate dielectrics are then removed from above the substrate. Dopant species which are opposite in type to the dopant species arranged within the semiconductor substrate are then implanted into exposed regions of the substrate to form source/drain regions directly adjacent the remaining gate conductor. Thereafter, an interlevel dielectric is deposited across the resulting topological surface of the semiconductor topography. Contacts are formed through the interlevel dielectric to the source/drain regions. Horizontally extending conductors are formed dielectrically spaced above the substrate to electrically link each of the contacts to a probe pad. Further, a conductor is formed which electrically links the gate conductor to a probe pad.
Various electrical tests may be performed on the test structure to determine the distinct properties of the transistor. For example, a voltage, VDD, may be applied to the probe pad that is electrically linked to one of the source/drain regions while the other source/drain region is grounded. A gate-to-source voltage, Vgs, which is greater than the transistor threshold voltage, VT, is simultaneously applied to the probe pad that is electrically linked to the gate conductor. The drive current, ID, of the now-operating transistor may then be measured by contacting a probe to the probe pad that is electrically linked to the drain.